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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc] - Rev 189

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Rev Log message Author Age Path
189 Fuller explanation of the build script given. jeremybennett 5116d 14h /openrisc
188 More rigorous testing of options. jeremybennett 5116d 15h /openrisc
187 Or1200 sprs FPU update julius 5118d 07h /openrisc
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5118d 10h /openrisc
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5118d 11h /openrisc
184 Fix the UART version of newlib. jeremybennett 5119d 15h /openrisc
183 Fix to setjmp, so it works. Some commenting tidy ups elsewhere. jeremybennett 5120d 07h /openrisc
182 Removed redundant code. jeremybennett 5120d 07h /openrisc
181 Updated, so only GCC tries to use parallel build. Redundant target for libgcc removed. jeremybennett 5120d 10h /openrisc
180 Rewritten to use namespace clean BSP in libgloss. Two versions of the library, one with, one without using the UART. jeremybennett 5120d 10h /openrisc
179 Code is now loaded from address 0, with section .vectors loaded before any other section. This provides a convenient mechanism for setting up the OR1K exception vectors. jeremybennett 5120d 10h /openrisc
178 Fixes a bug in prologue recognition without frame pointer. jeremybennett 5120d 10h /openrisc
177 Specified CPU type for or32, corrected templates for or32-*-elf*. Corrected specs in or32.h, added init and fini. Added support for newlib, including -mor32-newlib and -mor32-newlib-uart options. jeremybennett 5120d 10h /openrisc
176 Removing empty and redundant directory. jeremybennett 5125d 12h /openrisc
175 Moved orpmon into bootloaders julius 5125d 12h /openrisc
174 Consolidating all RTOS ports in one directory. jeremybennett 5125d 13h /openrisc
173 Consolidating all RTOS ports in one directory. jeremybennett 5125d 13h /openrisc
172 Information about this directory. jeremybennett 5125d 13h /openrisc
171 A new directory for ports of real time operating systems. jeremybennett 5125d 13h /openrisc
170 More detailed instructions. jeremybennett 5125d 13h /openrisc

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