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Rev Log message Author Age Path
373 ORPSoCv2 software update for compatibility with OR toolchain 1.0 julius 5046d 21h /openrisc
372 Toolchain install script uClibc variable update julius 5047d 00h /openrisc
371 Toolchain install script binutils commented out fix julius 5047d 00h /openrisc
370 Toolchain install script uclibc url fix julius 5047d 00h /openrisc
369 Toolchain build script binutils path fix julius 5047d 01h /openrisc
368 Toolchain script: adding sim url path julius 5047d 01h /openrisc
367 Fixup 1.0 release script julius 5047d 01h /openrisc
366 Version 1.0 toolchain script commit julius 5047d 01h /openrisc
365 Linux-2.6.34 patch update with updated USB ohs900 host julius 5049d 19h /openrisc
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5058d 18h /openrisc
363 ORPSoC's RTL code fixed to pass linting by Verilator.

ORPSoC's debug interface disabled for now in both RTL and System C top level.

Profiled building of cycle-accurate model now done correctly.		 julius 5059d 04h /openrisc
362 ORPSoCv2 verilator building working again. Board build fixes to follow julius 5060d 13h /openrisc
361 OPRSoCv2 - adding things left out in last check-in julius 5060d 18h /openrisc
360 First checkin of new ORPSoC set up - more to come, all but RTL tests temporarily broken julius 5060d 18h /openrisc
359 Removing duplicate OR1200 spec from docs/ path, original in or1200/doc should be used instead, also moving Japanese OR1200 spec to or1200/doc julius 5061d 01h /openrisc
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5061d 03h /openrisc
357 Tidied up commenting. jeremybennett 5061d 04h /openrisc
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 5061d 12h /openrisc
355 Adding CoreMark to ORPmon, updated Dhrystone test output julius 5061d 20h /openrisc
354 Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut

* sw/support/crt0.S: Tick timer interrupt to increment variable
now in place instead of calling customisable
interrupt vector handler

Changed all system frequencies in design to 50MHz.		 julius 5062d 18h /openrisc

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