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Rev Log message Author Age Path
444 Changes to ABI handling of varargs. jeremybennett 4960d 02h /openrisc
443 Work in progress on more efficient Ethernet. jeremybennett 4960d 06h /openrisc
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4960d 20h /openrisc
441 Changes for gdbserver. jeremybennett 4961d 03h /openrisc
440 Updated documentation to describe new Ethernet usage. jeremybennett 4961d 21h /openrisc
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 4964d 02h /openrisc
438 Fix to newlib header and library locations. jeremybennett 4967d 02h /openrisc
437 Or1ksim - ethernet peripheral update, working much better. julius 4969d 16h /openrisc
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4970d 16h /openrisc
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 4970d 17h /openrisc
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4973d 22h /openrisc
433 New single program interrupt test programs. jeremybennett 4975d 01h /openrisc
432 Updates to handle interrupts correctly. jeremybennett 4975d 02h /openrisc
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4977d 00h /openrisc
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4977d 22h /openrisc
429 or1ksim update - remove debug printfs from eth MDIO emulation function
and fix illegal instruction vector jump for invalid instructions.		 julius 4978d 02h /openrisc
428 or1ksim - adding preliminary PHY emulation to ethernet peripheral. julius 4980d 21h /openrisc
427 Fixes for C++ to correspond to fixes in uClibc. jeremybennett 4982d 06h /openrisc
426 ORPSoC update

Reverted back to previous OR1200 instruction cache.
(...which...)
Fixed or1200-except test failure on generic model.

ML501 build not passing or1200-except test. Tried disabling
burst on the bus (memory server doesn't support it yet) to
no avail. To be continued...		 julius 4983d 16h /openrisc
425 ORPSoC update:

GDB servers in VPI and System C model updated to deal with
packets gdb-7.2 sends.

Documentation updated.

Reference design tests can now be run in or1ksim (added rule
to sim/bin/Makefile). or1200-except doesn't appear to work
as illegal instruction error isn't causing jump to vector.

Updated Or1200 tests to report test success value and then
exit with value 0.		 julius 4983d 17h /openrisc

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