OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc] - Rev 454

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 5078d 20h /openrisc
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 5079d 07h /openrisc
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 5079d 15h /openrisc
451 More tidying up. jeremybennett 5083d 11h /openrisc
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5083d 15h /openrisc
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 5085d 12h /openrisc
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5085d 22h /openrisc
447 Updates to register order. jeremybennett 5086d 15h /openrisc
446 gdb-7.2 gdbserver updates. julius 5087d 10h /openrisc
445 gdbserver update to use kernel port ptrace register definitions. julius 5088d 07h /openrisc
444 Changes to ABI handling of varargs. jeremybennett 5088d 16h /openrisc
443 Work in progress on more efficient Ethernet. jeremybennett 5088d 19h /openrisc
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5089d 10h /openrisc
441 Changes for gdbserver. jeremybennett 5089d 16h /openrisc
440 Updated documentation to describe new Ethernet usage. jeremybennett 5090d 11h /openrisc
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5092d 15h /openrisc
438 Fix to newlib header and library locations. jeremybennett 5095d 16h /openrisc
437 Or1ksim - ethernet peripheral update, working much better. julius 5098d 06h /openrisc
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 5099d 06h /openrisc
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.		 julius 5099d 07h /openrisc

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.