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Rev Log message Author Age Path
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 5005d 09h /openrisc
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 5005d 11h /openrisc
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 5009d 13h /openrisc
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 5011d 15h /openrisc
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 5012d 01h /openrisc
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 5012d 10h /openrisc
451 More tidying up. jeremybennett 5016d 05h /openrisc
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 5016d 09h /openrisc
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.		 julius 5018d 06h /openrisc
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 5018d 16h /openrisc
447 Updates to register order. jeremybennett 5019d 10h /openrisc
446 gdb-7.2 gdbserver updates. julius 5020d 04h /openrisc
445 gdbserver update to use kernel port ptrace register definitions. julius 5021d 01h /openrisc
444 Changes to ABI handling of varargs. jeremybennett 5021d 10h /openrisc
443 Work in progress on more efficient Ethernet. jeremybennett 5021d 14h /openrisc
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 5022d 04h /openrisc
441 Changes for gdbserver. jeremybennett 5022d 10h /openrisc
440 Updated documentation to describe new Ethernet usage. jeremybennett 5023d 05h /openrisc
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.		 julius 5025d 10h /openrisc
438 Fix to newlib header and library locations. jeremybennett 5028d 10h /openrisc

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