OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_except.v] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5755d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7610d 15h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7860d 14h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1155 No functional change. Only added customization for exception vectors. lampret 7906d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8135d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8142d 15h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
993 Fixed IMMU bug. lampret 8148d 14h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
977 Added store buffer. lampret 8151d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8186d 18h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8340d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8354d 15h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8359d 09h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
595 Fixed 'the NPC single-step fix'. lampret 8364d 02h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8364d 09h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
571 Changed alignment exception EPCR. Not tested yet. lampret 8367d 19h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
570 Fixed order of syscall and range exceptions. lampret 8367d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8368d 10h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8379d 08h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_except.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.