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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Rev 1765

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Rev Log message Author Age Path
1765 root 5747d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
1220 Exception prefix configuration changed. simons 7658d 07h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
1206 Static exception prefix. lampret 7670d 21h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
1171 Added embedded memory QMEM. lampret 7820d 05h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7852d 17h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
1155 No functional change. Only added customization for exception vectors. lampret 7898d 22h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
788 Some of the warnings fixed. lampret 8286d 05h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8332d 16h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8346d 19h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8356d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8360d 14h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8371d 12h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_genpc.v

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