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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_ic_top.v] - Rev 1765

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Rev Log message Author Age Path
1765 root 5755d 17h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7674d 04h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
1171 Added embedded memory QMEM. lampret 7828d 00h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7860d 13h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8091d 20h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
788 Some of the warnings fixed. lampret 8294d 01h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8340d 11h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
636 Fixed combinational loops. lampret 8349d 20h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8354d 15h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8368d 10h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8379d 08h /or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_ic_top.v

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