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[/] [or1k/] [branches/] [branch_qmem/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5755d 17h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
1214	Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.	simons	7674d 04h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7860d 13h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7920d 15h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8091d 20h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8379d 08h	/or1k/branches/branch_qmem/or1200/rtl/verilog/or1200_spram_64x24.v