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[/] [or1k/] [branches/] [branch_speed_opt/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5607d 18h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_spram_2048x8.v
1164	This commit was manufactured by cvs2svn to create branch 'branch_speed_opt'.		7712d 14h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_spram_2048x8.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7772d 16h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_spram_2048x8.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7943d 21h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_spram_2048x8.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8231d 09h	/or1k/branches/branch_speed_opt/or1200/rtl/verilog/or1200_spram_2048x8.v