OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [cache/] [dcache_model.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5746d 05h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7234d 17h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7236d 10h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7249d 14h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7441d 04h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
1085 Bug fixed. simons 8048d 06h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8137d 19h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 8139d 10h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8181d 17h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
638 TLBTR CI bit is now working properly. simons 8340d 06h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
631 Real cache access is simulated now. simons 8343d 05h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8364d 14h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
428 cache configuration added markom 8392d 13h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8431d 18h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8517d 13h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8599d 23h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
54 Regular maintenance. lampret 8869d 20h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
26 Clean up. lampret 8977d 00h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c
5 Data and instruction cache simulation added. lampret 9041d 06h /or1k/branches/stable_0_1_x/or1ksim/cache/dcache_model.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.