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[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [mmu/] [dmmu.h] - Rev 1765

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1765 root 5754d 10h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7242d 22h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7244d 15h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7449d 10h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
430 dpfault and ipfault exceptions implemented markom 8400d 18h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
425 immu and dmmu configurations added markom 8400d 20h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
204 Added function prototypes to stop gcc from complaining erez 8482d 20h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
62 OR1K DMMU model. lampret 8827d 01h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 9049d 11h /or1k/branches/stable_0_1_x/or1ksim/mmu/dmmu.h

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