OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_1_x/] [or1ksim/] [testbench/] [except.S] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5755d 06h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
1356 This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'. 7243d 19h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
970 Testbench is now running on ORP architecture platform. simons 8154d 07h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 8156d 09h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 8156d 13h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8362d 06h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
475 l.jalr r9 is not used any more. simons 8393d 16h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
461 DTLBMISS and DPF exceptions are fixed in simulator. simons 8395d 06h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
441 Two instructions removed from reset wrapper to save space. simons 8400d 14h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
436 Copying from flash to ram only when there is 0xff on address 0. simons 8400d 15h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
413 some section changes markom 8405d 15h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
410 MMU test added. simons 8406d 13h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8406d 19h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
371 steps toward joining or32.c and opcode/or32.h of or1ksim and gdb; decode.c moved to or32.c markom 8416d 19h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8428d 17h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S
342 added exception vectors to support and modified section names markom 8429d 16h /or1k/branches/stable_0_1_x/or1ksim/testbench/except.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.