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[/] [or1k/] [tags/] [MW_0_8_9PRE7] - Rev 645

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Rev Log message Author Age Path
645 simple frame buffer peripheral with test added markom 8215d 17h /or1k/tags/MW_0_8_9PRE7
644 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8216d 13h /or1k/tags/MW_0_8_9PRE7
643 Quick bug fix. ivang 8216d 13h /or1k/tags/MW_0_8_9PRE7
642 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8216d 13h /or1k/tags/MW_0_8_9PRE7
641 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8216d 13h /or1k/tags/MW_0_8_9PRE7
640 Merge profiler and mprofiler with sim. ivang 8216d 14h /or1k/tags/MW_0_8_9PRE7
639 MMU cache inhibit bit test added. simons 8219d 05h /or1k/tags/MW_0_8_9PRE7
638 TLBTR CI bit is now working properly. simons 8219d 05h /or1k/tags/MW_0_8_9PRE7
637 Updated file names. lampret 8219d 06h /or1k/tags/MW_0_8_9PRE7
636 Fixed combinational loops. lampret 8219d 06h /or1k/tags/MW_0_8_9PRE7
635 Fixed Makefile bug. ivang 8219d 08h /or1k/tags/MW_0_8_9PRE7
634 configure.in : fixed to build start/Makefile
start.S : l.jalr r9 -> l.jr r9

Added missing files.		 ivang 8220d 09h /or1k/tags/MW_0_8_9PRE7
633 Bug fix in command line parser. ivang 8220d 10h /or1k/tags/MW_0_8_9PRE7
632 profiler and mprofiler merged into sim. ivang 8221d 05h /or1k/tags/MW_0_8_9PRE7
631 Real cache access is simulated now. simons 8222d 04h /or1k/tags/MW_0_8_9PRE7
630 some bug fixes in store buffer analysis markom 8222d 13h /or1k/tags/MW_0_8_9PRE7
629 typo fixed markom 8222d 16h /or1k/tags/MW_0_8_9PRE7
627 or32 restored markom 8222d 17h /or1k/tags/MW_0_8_9PRE7
626 store buffer added markom 8222d 17h /or1k/tags/MW_0_8_9PRE7
625 Bus error bug fixed. Cache routines added. simons 8223d 09h /or1k/tags/MW_0_8_9PRE7

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