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[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1382

Rev	Log message	Author	Age	Path
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7045d 13h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7080d 08h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7285d 02h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
631	Real cache access is simulated now.	simons	8187d 03h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
626	store buffer added	markom	8187d 16h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
428	cache configuration added	markom	8236d 11h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h
5	Data and instruction cache simulation added.	lampret	8885d 04h	/or1k/tags/nog_patch_34/or1ksim/cache/dcache_model.h