OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_46/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1350

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7090d 03h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7294d 22h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h
631 Real cache access is simulated now. simons 8196d 23h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h
626 store buffer added markom 8197d 12h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h
428 cache configuration added markom 8246d 06h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h
5 Data and instruction cache simulation added. lampret 8895d 00h /or1k/tags/nog_patch_46/or1ksim/cache/dcache_model.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.