OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [common/] [abstract.c] - Rev 1359

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1359 Pass private data in readfunc/writefunc callbacks nogj 7071d 07h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7071d 07h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1354 typing fixes phoenix 7079d 13h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7080d 10h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7093d 14h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1324 memory access functions fixes phoenix 7191d 06h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7197d 05h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7285d 05h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1244 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.		 hpanther 7452d 13h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7457d 00h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
1218 segfault when there is no memory context fix phoenix 7505d 03h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7981d 19h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
992 A bug when cache enabled and bus error comes fixed. simons 7983d 11h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
970 Testbench is now running on ORP architecture platform. simons 7989d 06h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
897 improved CUC GUI; pre/unroll bugs fixed markom 8018d 11h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8025d 17h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
882 Routine for adjusting read and write delay for devices added. simons 8028d 15h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
860 Added delayr and delayw variable initialization (default value 1) ivang 8073d 06h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
638 TLBTR CI bit is now working properly. simons 8184d 07h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c
631 Real cache access is simulated now. simons 8187d 06h /or1k/tags/nog_patch_47/or1ksim/cpu/common/abstract.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.