URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [mmu] - Rev 221

Rev	Log message	Author	Age	Path
221	major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup	markom	8313d 07h	/or1k/tags/nog_patch_50/or1ksim/mmu
204	Added function prototypes to stop gcc from complaining	erez	8347d 05h	/or1k/tags/nog_patch_50/or1ksim/mmu
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8390d 03h	/or1k/tags/nog_patch_50/or1ksim/mmu
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8472d 13h	/or1k/tags/nog_patch_50/or1ksim/mmu
74	Same as DMMU.	lampret	8679d 10h	/or1k/tags/nog_patch_50/or1ksim/mmu
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8679d 10h	/or1k/tags/nog_patch_50/or1ksim/mmu
62	OR1K DMMU model.	lampret	8691d 10h	/or1k/tags/nog_patch_50/or1ksim/mmu
18	or16 added, or1k renamed to or32.	lampret	8852d 10h	/or1k/tags/nog_patch_50/or1ksim/mmu
13	Rebuild of the generated files.	jrydberg	8913d 02h	/or1k/tags/nog_patch_50/or1ksim/mmu
7	Major update of the enviorment. Now uses autoconf and automake. The simulator uses readline aswell to get input from the user. A number of new files added, some modified. The libc directory is now called support.	jrydberg	8913d 02h	/or1k/tags/nog_patch_50/or1ksim/mmu
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	8913d 20h	/or1k/tags/nog_patch_50/or1ksim/mmu