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[/] [or1k/] [tags/] [nog_patch_55/] [or1ksim/] [cache/] [icache_model.h] - Rev 1778

Rev	Log message	Author	Age	Path
1765		root	5601d 17h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
1435	This commit was manufactured by cvs2svn to create tag 'nog_patch_55'.		7041d 23h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
1404	Move the function of ic_clock() to mtspr() and remove it	nogj	7042d 00h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7057d 03h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7091d 22h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7296d 16h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
631	Real cache access is simulated now.	simons	8198d 17h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
429	cache configuration added	markom	8248d 01h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8455d 10h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
76	regular update	lampret	8655d 08h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h
5	Data and instruction cache simulation added.	lampret	8896d 18h	/or1k/tags/nog_patch_55/or1ksim/cache/icache_model.h