URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_58/] [or1ksim/] [testbench/] [mmu.c] - Rev 970

Rev	Log message	Author	Age	Path
970	Testbench is now running on ORP architecture platform.	simons	8003d 23h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
957	Flash at 0x04000000 RAM at 0x00000000. Only MMU test works.	simons	8006d 00h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
639	MMU cache inhibit bit test added.	simons	8198d 23h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
600	No more low/high priority interrupts (PICPR removed). Added tick timer exception.	simons	8211d 22h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
509	unused var warning corrected	markom	8228d 07h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
480	RTL_SIM define added for shorter simulation runtime.	simons	8243d 06h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
466	EEAR is used for determing ITLB miss and IPF page address.	simons	8243d 22h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
457	Page size set to 8192.	simons	8248d 02h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
448	Permission test added.	simons	8249d 11h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
417	ITLB test tested on simulator.	simons	8253d 21h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
415	DTLB test tested on simulator.	simons	8254d 21h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
413	some section changes	markom	8255d 07h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
412	* empty log message *	simons	8255d 08h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c
410	MMU test added.	simons	8256d 04h	/or1k/tags/nog_patch_58/or1ksim/testbench/mmu.c