OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [dmmu.c] - Rev 600

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8192d 18h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
572 Some new bugs fixed. simons 8197d 20h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8204d 04h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8205d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
456 Page size bug fixed. simons 8228d 22h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
438 ITLB -> DTLB lapsus fixed. simons 8231d 03h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
430 dpfault and ipfault exceptions implemented markom 8232d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
429 cache configuration added markom 8232d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
425 immu and dmmu configurations added markom 8232d 04h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8259d 05h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed
markom 8357d 02h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8439d 12h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8646d 09h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
62 OR1K DMMU model. lampret 8658d 09h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8880d 19h /or1k/tags/nog_patch_61/or1ksim/mmu/dmmu.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.