OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_66] - Rev 1022

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8016d 16h /or1k/tags/nog_patch_66
1021 *** empty log message *** rherveille 8020d 19h /or1k/tags/nog_patch_66
1020 Fixed several bugs
Working version, tested on Bender hardware		 rherveille 8020d 19h /or1k/tags/nog_patch_66
1019 fixed some bugs detected by Bender hardware rherveille 8020d 19h /or1k/tags/nog_patch_66
1018 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8021d 01h /or1k/tags/nog_patch_66
1017 TX_BD_NUM register now contains a real number of transmit BDs (before this was n*2) simons 8021d 02h /or1k/tags/nog_patch_66
1016 64 bytes is the smallest packet size. simons 8021d 18h /or1k/tags/nog_patch_66
1015 Host type was not recognized. simons 8022d 04h /or1k/tags/nog_patch_66
1014 added _JBLEN definition for or1k ivang 8022d 18h /or1k/tags/nog_patch_66
1013 ORP architecture supported. simons 8022d 20h /or1k/tags/nog_patch_66
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 8023d 13h /or1k/tags/nog_patch_66
1010 Import ivang 8027d 16h /or1k/tags/nog_patch_66
1009 Import ivang 8027d 16h /or1k/tags/nog_patch_66
1008 Import ivang 8027d 17h /or1k/tags/nog_patch_66
1007 Import ivang 8027d 17h /or1k/tags/nog_patch_66
1006 Import ivang 8027d 17h /or1k/tags/nog_patch_66
1005 Import ivang 8027d 17h /or1k/tags/nog_patch_66
1004 Now every ramdisk image should have init program. simons 8028d 01h /or1k/tags/nog_patch_66
1003 cuc temporary files are deleted upon exiting markom 8028d 02h /or1k/tags/nog_patch_66
1002 Now every ramdisk image should have init program. simons 8028d 02h /or1k/tags/nog_patch_66

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.