URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_67] - Rev 993

Rev	Log message	Author	Age	Path
993	Fixed IMMU bug.	lampret	7996d 18h	/or1k/tags/nog_patch_67
992	A bug when cache enabled and bus error comes fixed.	simons	7997d 03h	/or1k/tags/nog_patch_67
991	Different memory controller.	simons	7997d 03h	/or1k/tags/nog_patch_67
990	Test is now complete.	simons	7997d 03h	/or1k/tags/nog_patch_67
989	c++ is making problems so, for now, it is excluded.	simons	7998d 11h	/or1k/tags/nog_patch_67
988	ORP architecture supported.	simons	7999d 03h	/or1k/tags/nog_patch_67
987	ORP architecture supported.	simons	7999d 10h	/or1k/tags/nog_patch_67
986	outputs out of function are not registered anymore	markom	7999d 11h	/or1k/tags/nog_patch_67
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	7999d 22h	/or1k/tags/nog_patch_67
984	Disable SB until it is tested	lampret	7999d 22h	/or1k/tags/nog_patch_67
983	First checkin	lampret	8000d 00h	/or1k/tags/nog_patch_67
982	Moved to sim/bin	lampret	8000d 00h	/or1k/tags/nog_patch_67
981	First checkin.	lampret	8000d 00h	/or1k/tags/nog_patch_67
980	Removed sim.tcl that shouldn't be here.	lampret	8000d 00h	/or1k/tags/nog_patch_67
979	Removed old test case binaries.	lampret	8000d 00h	/or1k/tags/nog_patch_67
978	Added variable delay for SRAM.	lampret	8000d 00h	/or1k/tags/nog_patch_67
977	Added store buffer.	lampret	8000d 00h	/or1k/tags/nog_patch_67
976	Added store buffer	lampret	8000d 00h	/or1k/tags/nog_patch_67
975	First checkin	lampret	8000d 00h	/or1k/tags/nog_patch_67
974	Enabled what works on or1ksim and disabled other tests.	lampret	8000d 02h	/or1k/tags/nog_patch_67