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[/] [or1k/] [tags/] [nog_patch_68] - Rev 998

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Rev Log message Author Age Path
998 added missing fout initialization markom 8000d 23h /or1k/tags/nog_patch_68
997 PRINTF should be used instead of printf; command redirection repaired markom 8001d 00h /or1k/tags/nog_patch_68
996 some minor bugs fixed markom 8001d 22h /or1k/tags/nog_patch_68
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8002d 06h /or1k/tags/nog_patch_68
993 Fixed IMMU bug. lampret 8002d 06h /or1k/tags/nog_patch_68
992 A bug when cache enabled and bus error comes fixed. simons 8002d 15h /or1k/tags/nog_patch_68
991 Different memory controller. simons 8002d 15h /or1k/tags/nog_patch_68
990 Test is now complete. simons 8002d 15h /or1k/tags/nog_patch_68
989 c++ is making problems so, for now, it is excluded. simons 8003d 23h /or1k/tags/nog_patch_68
988 ORP architecture supported. simons 8004d 15h /or1k/tags/nog_patch_68
987 ORP architecture supported. simons 8004d 22h /or1k/tags/nog_patch_68
986 outputs out of function are not registered anymore markom 8004d 23h /or1k/tags/nog_patch_68
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8005d 10h /or1k/tags/nog_patch_68
984 Disable SB until it is tested lampret 8005d 10h /or1k/tags/nog_patch_68
983 First checkin lampret 8005d 12h /or1k/tags/nog_patch_68
982 Moved to sim/bin lampret 8005d 12h /or1k/tags/nog_patch_68
981 First checkin. lampret 8005d 12h /or1k/tags/nog_patch_68
980 Removed sim.tcl that shouldn't be here. lampret 8005d 12h /or1k/tags/nog_patch_68
979 Removed old test case binaries. lampret 8005d 12h /or1k/tags/nog_patch_68
978 Added variable delay for SRAM. lampret 8005d 12h /or1k/tags/nog_patch_68

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