OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_70] - Rev 84

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
84 Update. lampret 8505d 21h /or1k/tags/nog_patch_70
83 Updates. lampret 8505d 21h /or1k/tags/nog_patch_70
82 Changed pctemp to pcnext. lampret 8505d 21h /or1k/tags/nog_patch_70
80 First import. lampret 8533d 15h /or1k/tags/nog_patch_70
79 Data and instruction cache simulation added. lampret 8535d 13h /or1k/tags/nog_patch_70
78 (i/d)tlb_status lampret 8659d 02h /or1k/tags/nog_patch_70
77 Regular update. lampret 8659d 03h /or1k/tags/nog_patch_70
76 regular update lampret 8659d 03h /or1k/tags/nog_patch_70
75 simgetstr added. eval_mem32 replaced with evalsim_mem32. lampret 8659d 03h /or1k/tags/nog_patch_70
74 Same as DMMU. lampret 8666d 02h /or1k/tags/nog_patch_70
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8666d 02h /or1k/tags/nog_patch_70
72 Added 'how to build GNU tools' lampret 8671d 03h /or1k/tags/nog_patch_70
71 Clean two typos. lampret 8676d 05h /or1k/tags/nog_patch_70
70 Basic setjmp/longjmp are ready. lampret 8676d 05h /or1k/tags/nog_patch_70
69 Sim debug. lampret 8678d 02h /or1k/tags/nog_patch_70
68 Added hook for l.sys 204. Changed SPR of flag (no more CCR) lampret 8678d 02h /or1k/tags/nog_patch_70
67 Added simulator "application load". lampret 8678d 02h /or1k/tags/nog_patch_70
66 Added another set of eval_ functions that should be used directly by simulator.
evalsim_ and setsim_ don't go through MMU transaltion mechanism.
lampret 8678d 02h /or1k/tags/nog_patch_70
65 Added DMMU stats. lampret 8678d 02h /or1k/tags/nog_patch_70
64 SPR bit definition moved to spr_defs.h. lampret 8678d 02h /or1k/tags/nog_patch_70

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.