OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_72/] - Rev 197

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
197 This is not used any more. simons 8341d 23h /or1k/tags/nog_patch_72
196 Configuration SPRs added. simons 8342d 00h /or1k/tags/nog_patch_72
195 New test added. simons 8342d 00h /or1k/tags/nog_patch_72
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8342d 08h /or1k/tags/nog_patch_72
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8342d 08h /or1k/tags/nog_patch_72
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8342d 17h /or1k/tags/nog_patch_72
191 Added UART jitter var to sim config chris 8343d 13h /or1k/tags/nog_patch_72
190 Added jitter initialization chris 8343d 13h /or1k/tags/nog_patch_72
189 fixed mode handling for tick facility chris 8343d 13h /or1k/tags/nog_patch_72
188 fixed PIC interrupt controller chris 8343d 13h /or1k/tags/nog_patch_72
187 minor change to clear pending exception chris 8343d 13h /or1k/tags/nog_patch_72
186 major change to UART structure chris 8343d 13h /or1k/tags/nog_patch_72
185 major change to UART code chris 8343d 13h /or1k/tags/nog_patch_72
184 modified decode for trace debugging chris 8343d 14h /or1k/tags/nog_patch_72
183 changed special case for PICSR chris 8343d 14h /or1k/tags/nog_patch_72
182 updated exception handling procedures chris 8343d 14h /or1k/tags/nog_patch_72
181 Added trace/stall commands chris 8343d 14h /or1k/tags/nog_patch_72
180 Updated debug. lampret 8343d 19h /or1k/tags/nog_patch_72
179 Sim run script lampret 8363d 12h /or1k/tags/nog_patch_72
178 Some test code lampret 8363d 12h /or1k/tags/nog_patch_72

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.