OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [cpu/] [or32] - Rev 1679

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1679 Remove useless memcpy() nogj 6749d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1678 Remove the ts_current hack by haveing the temporaries always shipped out before
any instruction that has the posibility to generate an exception
nogj 6749d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1677 Only ship a temporary out if it has been used as a destination register nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1676 Only move a register into a temporary if it has been used as a source register nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1675 Remove the unneeded local i from eval_insn_ops() nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1674 Move shipping the jump-to register to gen_j_reg(), where it belongs. nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1673 Move Condition to the correct place nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1672 Store instructions don't modify any register. Don't mark them as such in the
arch. definitions
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1671 Remove the unused addr parameter to the recompile_insn() function nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1670 Move the check for the link register from recompile_insn to the two jal
instructions that need it
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1669 Special case exception instructions only once nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1668 Create a def_op_t.h file that may be used to define arrays of function pointers,
pointing to the operation generation functions
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1667 Have store operations use op_1t.h and op_2t.h to generate the combination of
operations that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1666 Have load operations use op_1t.h and op_2t.h to generate the combination of
operations that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1665 Have mac operations use op_2t.h to generate the combination of operations that
operate on the different temporaries.
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1664 Have m{f,t}spr operations use op_1t.h and op_2t.h to generate the combination of
operations that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1663 Have compare operations use op_2t.h to generate the combination of operations
that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1662 Have sign extenstion operations use op_2t.h to generate the combination of
operations that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1661 Have arithetic operations use op_2t.h and op_3t.h to generate the combination of
operations that operate on the different temporaries
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32
1660 Create an op_3t.h file that automagically creates all the combinations of
operations depending on the number of tempraries availible. Move operations
that operate on three tempraries to the op_3t_op.h file from op.c
nogj 6749d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/cpu/or32

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.