OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [debug/] [Makefile.am] - Rev 1751

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1751 These are the changes to support Or1ksim 0.3.0rc2. Most significantly they provide GDB RSP support. They also fix 5 outstanding bugs and satisfy one new feature request. jeremybennett 5709d 07h /or1k/tags/rel-0-3-0-rc2/or1ksim/debug/Makefile.am
1748 These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.

Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals.
jeremybennett 5739d 03h /or1k/tags/rel-0-3-0-rc2/or1ksim/debug/Makefile.am
1745 These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. jeremybennett 5775d 02h /or1k/tags/rel-0-3-0-rc2/or1ksim/debug/Makefile.am
304 included VAPI in execution, but it is still not functioning; some cleanup in toplevel.c markom 8269d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/debug/Makefile.am
221 major changes to testbench; debug unit is moved to /debug; memory organization can be customized; UART from simons; overall cleanup markom 8284d 10h /or1k/tags/rel-0-3-0-rc2/or1ksim/debug/Makefile.am

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.