OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim] - Rev 461

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
461 DTLBMISS and DPF exceptions are fixed in simulator. simons 8275d 16h /or1k/tags/rel-0-3-0-rc2/or1ksim
460 excpt test removed except test added. simons 8275d 16h /or1k/tags/rel-0-3-0-rc2/or1ksim
459 This is replaced by except test. simons 8275d 16h /or1k/tags/rel-0-3-0-rc2/or1ksim
458 Align, bus error and range exception fixed. simons 8275d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim
457 Page size set to 8192. simons 8278d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim
456 Page size bug fixed. simons 8278d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim
455 For mc tests ivang 8279d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim
454 MC Tests. ivang 8279d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim
453 Also performs mc initialization. ivang 8279d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim
452 Added mc tests. ivang 8279d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim
451 each test should define its own LDFLAGS markom 8279d 03h /or1k/tags/rel-0-3-0-rc2/or1ksim
450 Exceptions are allways enabled. simons 8279d 05h /or1k/tags/rel-0-3-0-rc2/or1ksim
449 MMU test configuration. simons 8280d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim
448 Permission test added. simons 8280d 06h /or1k/tags/rel-0-3-0-rc2/or1ksim
447 ITLBMR register bit fields set in order. simons 8280d 07h /or1k/tags/rel-0-3-0-rc2/or1ksim
446 ITLBMR register bit fields set in order. simons 8280d 07h /or1k/tags/rel-0-3-0-rc2/or1ksim
445 Reading GPIO input reg now also returns values on output bits erez 8280d 08h /or1k/tags/rel-0-3-0-rc2/or1ksim
444 Added GPIO simulation erez 8280d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim
443 Text and data sections are put in ram. simons 8280d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim
442 VAPI can now accept requests for different device ids on the same stream erez 8281d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.