OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2] - Rev 16

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
16 Add support for systems without readline. To use GNU readline library,
use the `--enable-readline' option to the configure script.
jrydberg 8892d 17h /or1k/tags/rel-0-3-0-rc2
15 Initial revision. jrydberg 8929d 07h /or1k/tags/rel-0-3-0-rc2
14 First import. lampret 8929d 10h /or1k/tags/rel-0-3-0-rc2
13 Rebuild of the generated files. jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
12 Added information to the section about how to configure and compile
the package.
jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
11 Rebuild from configure.in. jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
10 Support for both architectures. Specify architecture with the
--target option.
jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
9 Added support for OpenRISC 100 and DLX. jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
8 Initial revision. jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
7 Major update of the enviorment. Now uses autoconf and automake. The
simulator uses readline aswell to get input from the user. A number of
new files added, some modified. The libc directory is now called support.
jrydberg 8930d 13h /or1k/tags/rel-0-3-0-rc2
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8931d 07h /or1k/tags/rel-0-3-0-rc2
5 Data and instruction cache simulation added. lampret 8931d 07h /or1k/tags/rel-0-3-0-rc2
4 no message lampret 8981d 11h /or1k/tags/rel-0-3-0-rc2
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.
cvs 9057d 00h /or1k/tags/rel-0-3-0-rc2
1 Standard project directories initialized by cvs2svn. 9057d 00h /or1k/tags/rel-0-3-0-rc2

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.