OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc3/] [or1ksim/] [testbench/] [Makefile.in] - Rev 516

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
516 except test files renamed markom 8229d 06h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
493 --enable-opt switch added to testbench configure markom 8243d 06h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
485 gdb.h moved to debug dir; except.ld renamed to default.ld markom 8244d 09h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
478 Started adding acv_gpio testbench erez 8245d 02h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
460 excpt test removed except test added. simons 8246d 18h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
451 each test should define its own LDFLAGS markom 8250d 04h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
424 memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory markom 8253d 06h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
413 some section changes markom 8257d 03h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
410 MMU test added. simons 8258d 00h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
409 some minor changes to or1ksim; Testbench except.s modified. Interrupt test almost finished for uart ACV. markom 8258d 07h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
385 check testbench now modified to work with new report output markom 8267d 03h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
381 number display is more strict with 0x prefix with hex numbers markom 8267d 06h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
380 all tests pass check markom 8267d 06h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8280d 05h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
342 added exception vectors to support and modified section names markom 8281d 04h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
310 make check working for all tests except cache markom 8285d 08h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
308 testbench now has make check markom 8286d 03h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
306 corrected lots of bugs markom 8286d 07h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
258 Added Ethernet test; renamed dma to dmatest; commented out missing pic.c erez 8293d 23h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in
229 Reran automake and autoconf erez 8301d 01h /or1k/tags/rel-0-3-0-rc3/or1ksim/testbench/Makefile.in

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.