OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] - Rev 794

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
794 Added again just recently removed full_case directive lampret 8141d 05h /or1k/tags/rel_1/or1200/rtl/verilog
791 Fixed some ports in instnatiations that were removed from the modules lampret 8141d 05h /or1k/tags/rel_1/or1200/rtl/verilog
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8141d 06h /or1k/tags/rel_1/or1200/rtl/verilog
788 Some of the warnings fixed. lampret 8141d 07h /or1k/tags/rel_1/or1200/rtl/verilog
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8142d 03h /or1k/tags/rel_1/or1200/rtl/verilog
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8142d 03h /or1k/tags/rel_1/or1200/rtl/verilog
776 Updated defines. lampret 8142d 03h /or1k/tags/rel_1/or1200/rtl/verilog
775 Optimized cache controller FSM. lampret 8142d 03h /or1k/tags/rel_1/or1200/rtl/verilog
774 Removed old files. lampret 8142d 03h /or1k/tags/rel_1/or1200/rtl/verilog
737 Added alternative for critical path in DU. lampret 8156d 21h /or1k/tags/rel_1/or1200/rtl/verilog
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8159d 21h /or1k/tags/rel_1/or1200/rtl/verilog
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8159d 21h /or1k/tags/rel_1/or1200/rtl/verilog
668 Lapsus fixed. simons 8184d 06h /or1k/tags/rel_1/or1200/rtl/verilog
663 No longer using async rst as sync reset for the counter. lampret 8186d 20h /or1k/tags/rel_1/or1200/rtl/verilog
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8187d 17h /or1k/tags/rel_1/or1200/rtl/verilog
636 Fixed combinational loops. lampret 8197d 02h /or1k/tags/rel_1/or1200/rtl/verilog
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8201d 21h /or1k/tags/rel_1/or1200/rtl/verilog
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8206d 14h /or1k/tags/rel_1/or1200/rtl/verilog
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8210d 08h /or1k/tags/rel_1/or1200/rtl/verilog
596 SR[TEE] should be zero after reset. lampret 8210d 13h /or1k/tags/rel_1/or1200/rtl/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.