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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1780

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1765 root 5590d 03h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
896 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8021d 04h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8021d 04h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8057d 10h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8128d 10h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
788 Some of the warnings fixed. lampret 8128d 11h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8129d 07h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
776 Updated defines. lampret 8129d 07h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
737 Added alternative for critical path in DU. lampret 8144d 02h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8147d 01h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8174d 22h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
636 Fixed combinational loops. lampret 8184d 06h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8197d 12h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8198d 18h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
569 Default ASIC configuration does not sample WB inputs. lampret 8202d 16h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8209d 01h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8213d 05h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8213d 18h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v

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