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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Rev 1780

Rev	Log message	Author	Age	Path
1765		root	5590d 03h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
896	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8021d 04h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
788	Some of the warnings fixed.	lampret	8128d 11h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8147d 00h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
636	Fixed combinational loops.	lampret	8184d 06h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8193d 18h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
596	SR[TEE] should be zero after reset.	lampret	8197d 16h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8198d 18h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8213d 18h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_sprs.v