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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog] - Rev 365

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Rev	Log message	Author	Age	Path
365	Added wb_cyc_o assignment after it was removed by accident.	lampret	8297d 08h	/or1k/tags/rel_1/or1200/rtl/verilog
360	Added OR1200_REGISTERED_INPUTS.	lampret	8299d 00h	/or1k/tags/rel_1/or1200/rtl/verilog
359	Added optional sampling of inputs.	lampret	8299d 00h	/or1k/tags/rel_1/or1200/rtl/verilog
358	Fixed virtual silicon single-port rams instantiation.	lampret	8299d 00h	/or1k/tags/rel_1/or1200/rtl/verilog
357	Fixed dbg_is_o assignment width.	lampret	8299d 00h	/or1k/tags/rel_1/or1200/rtl/verilog
356	Break point bug fixed	simons	8299d 03h	/or1k/tags/rel_1/or1200/rtl/verilog
354	Fixed width of du_except.	lampret	8299d 21h	/or1k/tags/rel_1/or1200/rtl/verilog
353	Cashes disabled.	simons	8300d 07h	/or1k/tags/rel_1/or1200/rtl/verilog
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8301d 10h	/or1k/tags/rel_1/or1200/rtl/verilog
351	Fixed some l.trap typos.	lampret	8301d 12h	/or1k/tags/rel_1/or1200/rtl/verilog
350	For GDB changed single stepping and disabled trap exception.	lampret	8301d 13h	/or1k/tags/rel_1/or1200/rtl/verilog
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8306d 12h	/or1k/tags/rel_1/or1200/rtl/verilog
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8306d 12h	/or1k/tags/rel_1/or1200/rtl/verilog
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8307d 20h	/or1k/tags/rel_1/or1200/rtl/verilog
316	Fixed exceptions.	lampret	8309d 18h	/or1k/tags/rel_1/or1200/rtl/verilog
271	Added missing endif	lampret	8314d 07h	/or1k/tags/rel_1/or1200/rtl/verilog
265	Modified virtual silicon instantiations.	lampret	8317d 03h	/or1k/tags/rel_1/or1200/rtl/verilog
220	Fixed parameters in generic sprams.	lampret	8328d 02h	/or1k/tags/rel_1/or1200/rtl/verilog
219	Fixed sensitivity list.	lampret	8329d 03h	/or1k/tags/rel_1/or1200/rtl/verilog
218	Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.	lampret	8329d 04h	/or1k/tags/rel_1/or1200/rtl/verilog

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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog] - Rev 365

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