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[/] [or1k/] [tags/] [rel_1/] [or1200] - Rev 571

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Rev Log message Author Age Path
571 Changed alignment exception EPCR. Not tested yet. lampret 8217d 01h /or1k/tags/rel_1/or1200
570 Fixed order of syscall and range exceptions. lampret 8217d 03h /or1k/tags/rel_1/or1200
569 Default ASIC configuration does not sample WB inputs. lampret 8217d 13h /or1k/tags/rel_1/or1200
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8217d 16h /or1k/tags/rel_1/or1200
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8223d 22h /or1k/tags/rel_1/or1200
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8228d 01h /or1k/tags/rel_1/or1200
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8228d 14h /or1k/tags/rel_1/or1200
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8258d 17h /or1k/tags/rel_1/or1200
401 *** empty log message *** simons 8262d 03h /or1k/tags/rel_1/or1200
400 force_dslot_fetch does not work - allways zero. simons 8262d 03h /or1k/tags/rel_1/or1200
399 Trap insn couses break after exits ex_insn. simons 8262d 03h /or1k/tags/rel_1/or1200
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8264d 23h /or1k/tags/rel_1/or1200
390 Changed instantiation name of VS RAMs. lampret 8265d 01h /or1k/tags/rel_1/or1200
387 Now FPGA and ASIC target are separate. lampret 8265d 03h /or1k/tags/rel_1/or1200
386 Fixed VS RAM instantiation - again. lampret 8265d 03h /or1k/tags/rel_1/or1200
370 Program counter divided to PPC and NPC. simons 8269d 01h /or1k/tags/rel_1/or1200
367 Changed DSR/DRR behavior and exception detection. lampret 8269d 14h /or1k/tags/rel_1/or1200
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8270d 09h /or1k/tags/rel_1/or1200
360 Added OR1200_REGISTERED_INPUTS. lampret 8272d 01h /or1k/tags/rel_1/or1200
359 Added optional sampling of inputs. lampret 8272d 01h /or1k/tags/rel_1/or1200

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