URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_1] - Rev 341

Rev	Log message	Author	Age	Path
341	added VAPI for uart; uart 16550 support, some bugs fixed	markom	8278d 15h	/or1k/tags/rel_1
340	Added hpint vector	lampret	8278d 16h	/or1k/tags/rel_1
339	Added setpc test	lampret	8278d 16h	/or1k/tags/rel_1
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8278d 16h	/or1k/tags/rel_1
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8278d 16h	/or1k/tags/rel_1
336	VAPI works	markom	8279d 11h	/or1k/tags/rel_1
335	some small bugs fixed	markom	8279d 12h	/or1k/tags/rel_1
334	removed vapi client file	markom	8279d 15h	/or1k/tags/rel_1
333	small bug fixed	markom	8279d 18h	/or1k/tags/rel_1
332	removed fixed irq numbering from pic.h; tick timer section added	markom	8279d 18h	/or1k/tags/rel_1
331	dependecy is required by history analisis	markom	8279d 19h	/or1k/tags/rel_1
330	Cache test	lampret	8279d 22h	/or1k/tags/rel_1
329	Now using macros from spr_defs.h	lampret	8279d 23h	/or1k/tags/rel_1
328	Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.	lampret	8280d 00h	/or1k/tags/rel_1
327	simulate_dc_mmu_load() was calling insn cache/mmu routines instead of data cache/mmu. Fixed.	lampret	8280d 00h	/or1k/tags/rel_1
326	More realistic default cache type.	lampret	8280d 00h	/or1k/tags/rel_1
325	minor ethernet testbench modifications	erez	8281d 04h	/or1k/tags/rel_1
324	added initial ethernet RX simulation (very simple for now)	erez	8281d 04h	/or1k/tags/rel_1
323	small fix	erez	8281d 04h	/or1k/tags/rel_1
322	IC test repaired.C	simons	8281d 08h	/or1k/tags/rel_1