URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_10] - Rev 88

Rev	Log message	Author	Age	Path
88	Update.	lampret	8504d 03h	/or1k/tags/rel_10
87	Files required for creation of html files.	lampret	8504d 04h	/or1k/tags/rel_10
86	Added dh command.	lampret	8504d 04h	/or1k/tags/rel_10
85	Added dumphex.	lampret	8504d 04h	/or1k/tags/rel_10
84	Update.	lampret	8504d 04h	/or1k/tags/rel_10
83	Updates.	lampret	8504d 04h	/or1k/tags/rel_10
82	Changed pctemp to pcnext.	lampret	8504d 04h	/or1k/tags/rel_10
80	First import.	lampret	8531d 23h	/or1k/tags/rel_10
79	Data and instruction cache simulation added.	lampret	8533d 20h	/or1k/tags/rel_10
78	(i/d)tlb_status	lampret	8657d 10h	/or1k/tags/rel_10
77	Regular update.	lampret	8657d 10h	/or1k/tags/rel_10
76	regular update	lampret	8657d 10h	/or1k/tags/rel_10
75	simgetstr added. eval_mem32 replaced with evalsim_mem32.	lampret	8657d 10h	/or1k/tags/rel_10
74	Same as DMMU.	lampret	8664d 09h	/or1k/tags/rel_10
73	Fixed all bugs. Now more or less works. IMMU still has some problems (exception start).	lampret	8664d 09h	/or1k/tags/rel_10
72	Added 'how to build GNU tools'	lampret	8669d 10h	/or1k/tags/rel_10
71	Clean two typos.	lampret	8674d 12h	/or1k/tags/rel_10
70	Basic setjmp/longjmp are ready.	lampret	8674d 12h	/or1k/tags/rel_10
69	Sim debug.	lampret	8676d 09h	/or1k/tags/rel_10
68	Added hook for l.sys 204. Changed SPR of flag (no more CCR)	lampret	8676d 10h	/or1k/tags/rel_10