URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_10] - Rev 996

Rev	Log message	Author	Age	Path
996	some minor bugs fixed	markom	7997d 19h	/or1k/tags/rel_10
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	7998d 03h	/or1k/tags/rel_10
993	Fixed IMMU bug.	lampret	7998d 03h	/or1k/tags/rel_10
992	A bug when cache enabled and bus error comes fixed.	simons	7998d 12h	/or1k/tags/rel_10
991	Different memory controller.	simons	7998d 12h	/or1k/tags/rel_10
990	Test is now complete.	simons	7998d 12h	/or1k/tags/rel_10
989	c++ is making problems so, for now, it is excluded.	simons	7999d 20h	/or1k/tags/rel_10
988	ORP architecture supported.	simons	8000d 12h	/or1k/tags/rel_10
987	ORP architecture supported.	simons	8000d 19h	/or1k/tags/rel_10
986	outputs out of function are not registered anymore	markom	8000d 20h	/or1k/tags/rel_10
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8001d 07h	/or1k/tags/rel_10
984	Disable SB until it is tested	lampret	8001d 07h	/or1k/tags/rel_10
983	First checkin	lampret	8001d 09h	/or1k/tags/rel_10
982	Moved to sim/bin	lampret	8001d 09h	/or1k/tags/rel_10
981	First checkin.	lampret	8001d 09h	/or1k/tags/rel_10
980	Removed sim.tcl that shouldn't be here.	lampret	8001d 09h	/or1k/tags/rel_10
979	Removed old test case binaries.	lampret	8001d 09h	/or1k/tags/rel_10
978	Added variable delay for SRAM.	lampret	8001d 09h	/or1k/tags/rel_10
977	Added store buffer.	lampret	8001d 09h	/or1k/tags/rel_10
976	Added store buffer	lampret	8001d 09h	/or1k/tags/rel_10