URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Rev 1200

Rev	Log message	Author	Age	Path
1200	mbist signals updated according to newest convention	markom	7569d 04h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v
1184	Scan signals mess fixed.	simons	7627d 19h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v
1179	BIST interface added for Artisan memory instances.	simons	7635d 22h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7762d 11h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7933d 16h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8221d 04h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_64x24.v