URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_16] - Rev 200

Rev	Log message	Author	Age	Path
200	Initial import	simons	8375d 04h	/or1k/tags/rel_16
199	Initial import	simons	8375d 05h	/or1k/tags/rel_16
198	Moved from testbench.old	simons	8377d 16h	/or1k/tags/rel_16
197	This is not used any more.	simons	8377d 16h	/or1k/tags/rel_16
196	Configuration SPRs added.	simons	8377d 17h	/or1k/tags/rel_16
195	New test added.	simons	8377d 17h	/or1k/tags/rel_16
194	Fixed a bug for little endian architectures. Could cause a hang of gdb under some circumstances.	chris	8378d 01h	/or1k/tags/rel_16
193	Declared RISCOP.RESET to be volatile so that -O2 optimization would not optimize away the correct behavior by trying to be too clever.	chris	8378d 01h	/or1k/tags/rel_16
192	Removed GlobalMode reference causing problems for --disable-debugmod option.	chris	8378d 10h	/or1k/tags/rel_16
191	Added UART jitter var to sim config	chris	8379d 06h	/or1k/tags/rel_16
190	Added jitter initialization	chris	8379d 06h	/or1k/tags/rel_16
189	fixed mode handling for tick facility	chris	8379d 07h	/or1k/tags/rel_16
188	fixed PIC interrupt controller	chris	8379d 07h	/or1k/tags/rel_16
187	minor change to clear pending exception	chris	8379d 07h	/or1k/tags/rel_16
186	major change to UART structure	chris	8379d 07h	/or1k/tags/rel_16
185	major change to UART code	chris	8379d 07h	/or1k/tags/rel_16
184	modified decode for trace debugging	chris	8379d 07h	/or1k/tags/rel_16
183	changed special case for PICSR	chris	8379d 07h	/or1k/tags/rel_16
182	updated exception handling procedures	chris	8379d 07h	/or1k/tags/rel_16
181	Added trace/stall commands	chris	8379d 07h	/or1k/tags/rel_16