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[/] [or1k/] [tags/] [rel_17/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Rev 1780

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1765 root 5601d 19h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1215 This commit was manufactured by cvs2svn to create tag 'rel_17'. 7520d 06h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7520d 06h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1209 Fixed instantiation name. lampret 7524d 18h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1175 Added three missing wire declarations. No functional changes. lampret 7671d 17h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1171 Added embedded memory QMEM. lampret 7674d 02h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7706d 15h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7886d 09h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7937d 22h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
977 Added store buffer. lampret 7997d 22h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8032d 20h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
788 Some of the warnings fixed. lampret 8140d 03h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8186d 13h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
636 Fixed combinational loops. lampret 8195d 22h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8200d 17h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8210d 10h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8225d 10h /or1k/tags/rel_17/or1200/rtl/verilog/or1200_top.v

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