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[/] [or1k/] [tags/] [rel_2/] [or1200/] [rtl] - Rev 778

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Rev Log message Author Age Path
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8141d 11h /or1k/tags/rel_2/or1200/rtl
777 Changed define name from OR1200_MEM2REG_FAST to OR1200_IMPL_MEM2REG2 lampret 8141d 12h /or1k/tags/rel_2/or1200/rtl
776 Updated defines. lampret 8141d 12h /or1k/tags/rel_2/or1200/rtl
775 Optimized cache controller FSM. lampret 8141d 12h /or1k/tags/rel_2/or1200/rtl
774 Removed old files. lampret 8141d 12h /or1k/tags/rel_2/or1200/rtl
737 Added alternative for critical path in DU. lampret 8156d 06h /or1k/tags/rel_2/or1200/rtl
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8159d 05h /or1k/tags/rel_2/or1200/rtl
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8159d 05h /or1k/tags/rel_2/or1200/rtl
668 Lapsus fixed. simons 8183d 15h /or1k/tags/rel_2/or1200/rtl
663 No longer using async rst as sync reset for the counter. lampret 8186d 05h /or1k/tags/rel_2/or1200/rtl
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8187d 02h /or1k/tags/rel_2/or1200/rtl
636 Fixed combinational loops. lampret 8196d 11h /or1k/tags/rel_2/or1200/rtl
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8201d 06h /or1k/tags/rel_2/or1200/rtl
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8205d 23h /or1k/tags/rel_2/or1200/rtl
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8209d 17h /or1k/tags/rel_2/or1200/rtl
596 SR[TEE] should be zero after reset. lampret 8209d 21h /or1k/tags/rel_2/or1200/rtl
595 Fixed 'the NPC single-step fix'. lampret 8210d 16h /or1k/tags/rel_2/or1200/rtl
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8210d 23h /or1k/tags/rel_2/or1200/rtl
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8214d 01h /or1k/tags/rel_2/or1200/rtl
571 Changed alignment exception EPCR. Not tested yet. lampret 8214d 10h /or1k/tags/rel_2/or1200/rtl

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