URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21/] - Rev 981

Rev	Log message	Author	Age	Path
981	First checkin.	lampret	8002d 06h	/or1k/tags/rel_21
980	Removed sim.tcl that shouldn't be here.	lampret	8002d 06h	/or1k/tags/rel_21
979	Removed old test case binaries.	lampret	8002d 06h	/or1k/tags/rel_21
978	Added variable delay for SRAM.	lampret	8002d 06h	/or1k/tags/rel_21
977	Added store buffer.	lampret	8002d 06h	/or1k/tags/rel_21
976	Added store buffer	lampret	8002d 06h	/or1k/tags/rel_21
975	First checkin	lampret	8002d 06h	/or1k/tags/rel_21
974	Enabled what works on or1ksim and disabled other tests.	lampret	8002d 08h	/or1k/tags/rel_21
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8004d 13h	/or1k/tags/rel_21
972	Interrupt suorces fixed.	simons	8004d 13h	/or1k/tags/rel_21
971	Now even keyboard test passes.	simons	8004d 16h	/or1k/tags/rel_21
970	Testbench is now running on ORP architecture platform.	simons	8005d 05h	/or1k/tags/rel_21
969	Checking in except directory.	lampret	8005d 20h	/or1k/tags/rel_21
968	Checking in utils directory.	lampret	8005d 20h	/or1k/tags/rel_21
967	Checking in mul directory.	lampret	8005d 20h	/or1k/tags/rel_21
966	Checking in cbasic directory.	lampret	8005d 20h	/or1k/tags/rel_21
965	Checking in basic directory.	lampret	8005d 20h	/or1k/tags/rel_21
964	Checking in support directory.	lampret	8005d 20h	/or1k/tags/rel_21
962	Fixed Xilinx trace buffer address. REported by Taylor Su.	lampret	8005d 20h	/or1k/tags/rel_21
961	uart16550 RTL files renamed/added/removed.	lampret	8005d 20h	/or1k/tags/rel_21