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[/] [or1k/] [tags/] [rel_21/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Rev 958

Rev	Log message	Author	Age	Path
958	Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.	lampret	8038d 09h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
942	Delayed external access at page crossing.	lampret	8040d 10h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
788	Some of the warnings fixed.	lampret	8176d 00h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
660	Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.	lampret	8222d 11h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
636	Fixed combinational loops.	lampret	8231d 19h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8236d 14h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8250d 09h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8261d 07h	/or1k/tags/rel_21/or1200/rtl/verilog/or1200_immu_top.v