URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_21] - Rev 992

Rev	Log message	Author	Age	Path
992	A bug when cache enabled and bus error comes fixed.	simons	7999d 18h	/or1k/tags/rel_21
991	Different memory controller.	simons	7999d 18h	/or1k/tags/rel_21
990	Test is now complete.	simons	7999d 18h	/or1k/tags/rel_21
989	c++ is making problems so, for now, it is excluded.	simons	8001d 02h	/or1k/tags/rel_21
988	ORP architecture supported.	simons	8001d 17h	/or1k/tags/rel_21
987	ORP architecture supported.	simons	8002d 01h	/or1k/tags/rel_21
986	outputs out of function are not registered anymore	markom	8002d 01h	/or1k/tags/rel_21
985	DTLB translation doesn't work on or1ksim when IC/DC enabled.	lampret	8002d 13h	/or1k/tags/rel_21
984	Disable SB until it is tested	lampret	8002d 13h	/or1k/tags/rel_21
983	First checkin	lampret	8002d 15h	/or1k/tags/rel_21
982	Moved to sim/bin	lampret	8002d 15h	/or1k/tags/rel_21
981	First checkin.	lampret	8002d 15h	/or1k/tags/rel_21
980	Removed sim.tcl that shouldn't be here.	lampret	8002d 15h	/or1k/tags/rel_21
979	Removed old test case binaries.	lampret	8002d 15h	/or1k/tags/rel_21
978	Added variable delay for SRAM.	lampret	8002d 15h	/or1k/tags/rel_21
977	Added store buffer.	lampret	8002d 15h	/or1k/tags/rel_21
976	Added store buffer	lampret	8002d 15h	/or1k/tags/rel_21
975	First checkin	lampret	8002d 15h	/or1k/tags/rel_21
974	Enabled what works on or1ksim and disabled other tests.	lampret	8002d 17h	/or1k/tags/rel_21
973	generated cuc top scheduler builds without syntax errors; not tested yet	markom	8004d 21h	/or1k/tags/rel_21