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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] - Rev 597

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Rev Log message Author Age Path
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8212d 05h /or1k/tags/rel_25/or1200/rtl
596 SR[TEE] should be zero after reset. lampret 8212d 10h /or1k/tags/rel_25/or1200/rtl
595 Fixed 'the NPC single-step fix'. lampret 8213d 05h /or1k/tags/rel_25/or1200/rtl
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8213d 12h /or1k/tags/rel_25/or1200/rtl
573 Fixed module name when compiling with OR1200_XILINX_RAM32X1D lampret 8216d 13h /or1k/tags/rel_25/or1200/rtl
571 Changed alignment exception EPCR. Not tested yet. lampret 8216d 22h /or1k/tags/rel_25/or1200/rtl
570 Fixed order of syscall and range exceptions. lampret 8217d 00h /or1k/tags/rel_25/or1200/rtl
569 Default ASIC configuration does not sample WB inputs. lampret 8217d 10h /or1k/tags/rel_25/or1200/rtl
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8217d 13h /or1k/tags/rel_25/or1200/rtl
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8223d 19h /or1k/tags/rel_25/or1200/rtl
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8227d 22h /or1k/tags/rel_25/or1200/rtl
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8228d 11h /or1k/tags/rel_25/or1200/rtl
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8258d 14h /or1k/tags/rel_25/or1200/rtl
401 *** empty log message *** simons 8262d 01h /or1k/tags/rel_25/or1200/rtl
400 force_dslot_fetch does not work - allways zero. simons 8262d 01h /or1k/tags/rel_25/or1200/rtl
399 Trap insn couses break after exits ex_insn. simons 8262d 01h /or1k/tags/rel_25/or1200/rtl
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8264d 20h /or1k/tags/rel_25/or1200/rtl
390 Changed instantiation name of VS RAMs. lampret 8264d 22h /or1k/tags/rel_25/or1200/rtl
387 Now FPGA and ASIC target are separate. lampret 8265d 00h /or1k/tags/rel_25/or1200/rtl
386 Fixed VS RAM instantiation - again. lampret 8265d 00h /or1k/tags/rel_25/or1200/rtl

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