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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 1083

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Rev	Log message	Author	Age	Path
1083	SB mem width fixed.	simons	7948d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
1079	RAMs wrong connected to the BIST scan chain.	mohor	7957d 18h	/or1k/tags/rel_25/or1200/rtl/verilog
1078	Previous check-in was done by mistake.	mohor	7957d 19h	/or1k/tags/rel_25/or1200/rtl/verilog
1077	Signal scanb_sen renamed to scanb_en.	mohor	7957d 19h	/or1k/tags/rel_25/or1200/rtl/verilog
1069	Signal scanb_eni renamed to scanb_en	mohor	7961d 12h	/or1k/tags/rel_25/or1200/rtl/verilog
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7968d 14h	/or1k/tags/rel_25/or1200/rtl/verilog
1055	Removed obsolete comment.	lampret	8000d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
1054	Fixed a combinational loop.	lampret	8000d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
1053	Disabled cache inhibit atttribute.	lampret	8000d 07h	/or1k/tags/rel_25/or1200/rtl/verilog
1038	Fixed a typo, reported by Taylor Su.	lampret	8007d 15h	/or1k/tags/rel_25/or1200/rtl/verilog
1035	Added optional l.div/l.divu insns. By default they are disabled.	lampret	8008d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
1033	If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY].	lampret	8008d 15h	/or1k/tags/rel_25/or1200/rtl/verilog
1032	Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.	lampret	8009d 05h	/or1k/tags/rel_25/or1200/rtl/verilog
1023	Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v.	lampret	8012d 10h	/or1k/tags/rel_25/or1200/rtl/verilog
1022	As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.	lampret	8012d 12h	/or1k/tags/rel_25/or1200/rtl/verilog
1011	Removed some commented RTL. Fixed SR/ESR flag bug.	lampret	8019d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
994	Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board.	lampret	8025d 08h	/or1k/tags/rel_25/or1200/rtl/verilog
993	Fixed IMMU bug.	lampret	8025d 08h	/or1k/tags/rel_25/or1200/rtl/verilog
984	Disable SB until it is tested	lampret	8028d 12h	/or1k/tags/rel_25/or1200/rtl/verilog
977	Added store buffer.	lampret	8028d 14h	/or1k/tags/rel_25/or1200/rtl/verilog

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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 1083

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