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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 536

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Rev Log message Author Age Path
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8252d 08h /or1k/tags/rel_25/or1200/rtl/verilog
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8256d 11h /or1k/tags/rel_25/or1200/rtl/verilog
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8257d 00h /or1k/tags/rel_25/or1200/rtl/verilog
402 Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32 lampret 8287d 04h /or1k/tags/rel_25/or1200/rtl/verilog
401 *** empty log message *** simons 8290d 14h /or1k/tags/rel_25/or1200/rtl/verilog
400 force_dslot_fetch does not work - allways zero. simons 8290d 14h /or1k/tags/rel_25/or1200/rtl/verilog
399 Trap insn couses break after exits ex_insn. simons 8290d 14h /or1k/tags/rel_25/or1200/rtl/verilog
391 Fixed except_stop width and fixed EX PC for 1400444f no-ops. lampret 8293d 09h /or1k/tags/rel_25/or1200/rtl/verilog
390 Changed instantiation name of VS RAMs. lampret 8293d 11h /or1k/tags/rel_25/or1200/rtl/verilog
387 Now FPGA and ASIC target are separate. lampret 8293d 13h /or1k/tags/rel_25/or1200/rtl/verilog
386 Fixed VS RAM instantiation - again. lampret 8293d 13h /or1k/tags/rel_25/or1200/rtl/verilog
370 Program counter divided to PPC and NPC. simons 8297d 11h /or1k/tags/rel_25/or1200/rtl/verilog
367 Changed DSR/DRR behavior and exception detection. lampret 8298d 00h /or1k/tags/rel_25/or1200/rtl/verilog
365 Added wb_cyc_o assignment after it was removed by accident. lampret 8298d 19h /or1k/tags/rel_25/or1200/rtl/verilog
360 Added OR1200_REGISTERED_INPUTS. lampret 8300d 11h /or1k/tags/rel_25/or1200/rtl/verilog
359 Added optional sampling of inputs. lampret 8300d 11h /or1k/tags/rel_25/or1200/rtl/verilog
358 Fixed virtual silicon single-port rams instantiation. lampret 8300d 11h /or1k/tags/rel_25/or1200/rtl/verilog
357 Fixed dbg_is_o assignment width. lampret 8300d 11h /or1k/tags/rel_25/or1200/rtl/verilog
356 Break point bug fixed simons 8300d 14h /or1k/tags/rel_25/or1200/rtl/verilog
354 Fixed width of du_except. lampret 8301d 08h /or1k/tags/rel_25/or1200/rtl/verilog

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