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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 597

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Rev	Log message	Author	Age	Path
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8275d 03h	/or1k/tags/rel_25/or1200/rtl/verilog
596	SR[TEE] should be zero after reset.	lampret	8275d 08h	/or1k/tags/rel_25/or1200/rtl/verilog
595	Fixed 'the NPC single-step fix'.	lampret	8276d 03h	/or1k/tags/rel_25/or1200/rtl/verilog
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8276d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8279d 11h	/or1k/tags/rel_25/or1200/rtl/verilog
571	Changed alignment exception EPCR. Not tested yet.	lampret	8279d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
570	Fixed order of syscall and range exceptions.	lampret	8279d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
569	Default ASIC configuration does not sample WB inputs.	lampret	8280d 08h	/or1k/tags/rel_25/or1200/rtl/verilog
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8280d 11h	/or1k/tags/rel_25/or1200/rtl/verilog
536	Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.	lampret	8286d 17h	/or1k/tags/rel_25/or1200/rtl/verilog
512	Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target.	lampret	8290d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8291d 09h	/or1k/tags/rel_25/or1200/rtl/verilog
402	Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32	lampret	8321d 12h	/or1k/tags/rel_25/or1200/rtl/verilog
401	* empty log message *	simons	8324d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
400	force_dslot_fetch does not work - allways zero.	simons	8324d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
399	Trap insn couses break after exits ex_insn.	simons	8324d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
391	Fixed except_stop width and fixed EX PC for 1400444f no-ops.	lampret	8327d 18h	/or1k/tags/rel_25/or1200/rtl/verilog
390	Changed instantiation name of VS RAMs.	lampret	8327d 20h	/or1k/tags/rel_25/or1200/rtl/verilog
387	Now FPGA and ASIC target are separate.	lampret	8327d 22h	/or1k/tags/rel_25/or1200/rtl/verilog
386	Fixed VS RAM instantiation - again.	lampret	8327d 22h	/or1k/tags/rel_25/or1200/rtl/verilog

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[/] [or1k/] [tags/] [rel_25/] [or1200/] [rtl/] [verilog] - Rev 597

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